The present invention relates to semiconductor devices and the fabrication of semiconductor devices, and more particularly to semiconductor devices in 32 nm technology nodes and beyond.
In the field of semiconductor technology, aluminum or aluminum alloy is mainly used in high-k metal gate (HKMG) process technology nodes at 32 nm and below (e.g., 28 nm). The use of aluminum or aluminum alloy for metal gate electrodes has cost and performance advantages. The aluminum gate chemical mechanical polishing (CMP) process is a very important process for manufacturing high-k metal gate transistors with aluminum gates.
In order to increase the gap filling space, a CMP process of aluminum gate structures typically includes two CMP steps: a CMP process for N-type aluminum gate transistors and a CMP process for P-type aluminum gate transistors.
Since a conventional CMP process utilizes a polish slurry that has a polysilicon removal rate greater than the aluminum removal rate, the polysilicon gate tends to be over-polished. Furthermore, an over-polishing of the polysilicon gate may occur during the CMP process of the aluminum gate of the N-type transistors.
FIG. 1 is a simplified cross-sectional view illustrating process steps of forming a semiconductor structure. FIG. 1 includes a top part, a middle part, and a bottom part. As shown in FIG. 1, the top part shows as having three transistor regions 101A, 101B, and 101C that are separated by an interlayer dielectric layer 101D after a CMP process has been performed on the interlayer dielectric layer. Transistor region 101A is denoted a P-type aluminum gate transistor region; transistor region 101B is denoted an N-type aluminum gate transistor region; and transistor region 101C is denoted a polysilicon gate transistor region. The middle part shows that there is a height loss 121 in the N-type aluminum gate transistor region and in the polysilicon gate transistor gate region after a CMP process has been performed on the P-type aluminum gate transistor region. The bottom part shows that there is a further height loss 122 after a chemical mechanical polishing process has been performed on the N-type aluminum gate region. As can be clearly seen, the height of the polysilicon gate transistor region is significantly reduced due to over-polishing, which seriously affects the performance and yield of the manufactured semiconductor device.
Thus, the conventional CMP process of planarizing the metal gate (e.g., aluminum) uses a slurry that has a higher metal removal rate than that of the polysilicon, resulting in an over-polishing of the polysilicon gate and impacting the performance and yield of the semiconductor device.
In view of the foregoing, there is a need for a novel method and apparatus for manufacturing a semiconductor device that can overcome the deficiencies of the prior art.